Synopsys Design Compiler Tutorial — 2021 ((link))

[ Read/Analyze RTL ] ──> [ Define Design Constraints ] ──> [ Compile/Optimize ] ──> [ Analyze Reports ] ──> [ Export Netlist ] Phase 1: Reading and Analyzing the RTL

symbol_library : Used for graphical schematic viewing ( .sdb files). synopsys design compiler tutorial 2021

# Assume external chip paths take 30% of clock cycle set_input_delay 3.0 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 3.0 -clock sys_clk [all_outputs] Use code with caution. Design Environment Constraints [ Read/Analyze RTL ] ──> [ Define Design

Pro tip for 2021: Use dc_shell -64bit -legacy_ui if you prefer the classic Tcl prompt over the new Python-driven interface. synopsys design compiler tutorial 2021

set_clock_uncertainty -setup 0.050 [get_clocks core_clk] set_clock_uncertainty -hold 0.050 [get_clocks core_clk]

report_timing > ./reports/timing.rpt