A distinguishing feature of the XUP DSP Primer is its reliance on using MathWorks Simulink and the Xilinx System Generator for DSP.
Real-world DSP algorithms operate on continuous floating-point numbers. FPGAs can implement floating-point hardware, but it is resource-intensive. Therefore, fixed-point arithmetic is preferred for performance and efficiency. Xilinx University Program - DSP for FPGA Primer...
A typical 32-tap FIR filter on a 200 MHz ARM Cortex-M takes ~32 cycles per sample. On an FPGA using the XUP primer’s systolic architecture, it takes 1 clock cycle for all 32 taps. That’s a 32x speedup—without increasing clock frequency. A distinguishing feature of the XUP DSP Primer
The is an invaluable resource for students and academics. By combining theoretical knowledge with hands-on lab experience, it equips learners with the necessary skills to excel in the fast-evolving field of hardware-accelerated digital signal processing. That’s a 32x speedup—without increasing clock frequency