Synopsys Timing Constraints And Optimization User Guide 2021

: Moving registers across combinational logic boundaries to balance path delays without changing the design’s functionality.

The guide provides extensive coverage on exceptions, which override the default single-cycle timing analysis: synopsys timing constraints and optimization user guide 2021

create_clock -name clk -period 10 -waveform 0 5 set_input_delay -max 3 -clock clk [get_ports input_port] set_output_delay -max 2 -clock clk [get_ports output_port] : Moving registers across combinational logic boundaries to

: set_max_area , set_max_dynamic_power , and set_max_leakage_power are used to drive the tool toward smaller or more efficient implementations. and area targets. Critical Path Resynthesis

: Selects specific physical cells from the target technology library (.lib) that fulfill delay, power, and area targets. Critical Path Resynthesis